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ordering number : en * 4435a 63095ha (ot)/n1194jn/d1192jn no. 4435-1/29 overview the lc587004, LC587006 and lc587008 are 80-pin low- voltage cmos 4-bit microprocessors that include lcd drivers, 2 kb ram and 8, 12, or 16 kb rom on chip. these microprocessors correspond to the earlier lc5870 series with the 256 by 4-bit on-chip ram expanded to a 512 by 4-bit capacity. applications system control and lcd display in cd players, cameras and radio tuners system control and lcd display in miniature test equipment and consumer health care products these microprocessors are optimal for products that include lcd displays and, in particular, battery operated products. remote controllers for vcrs and audio equipment functions program rom: 8064 16 bits (lc587008), 6144 16 bits (LC587006) and 4096 16 bits (lc587004) ram: 512 4 bits on chip all instructions execute in a single cycle cycle time and operating voltage ranges 2 ? cycle time: v dd = 2.8 to 6.0 v 10 ? cycle time: v dd = 2.2 to 6.0 v 122 ? cycle time: v dd = 2.0 to 6.0 v rich set of halt/hold mode clearing and interrupt functions eight halt mode clearing functions seven hold mode clearing functions seven interrupt functions (all of which can be used as external interrupts) subroutines can be nested up to eight levels (including interrupt handling) built-in watchdog timer function powerful hardware for improved processing capacity built-in segment pla and segment decoder: lcd panel segments can be handled with no software processing of the lcd driver outputs. also, the lcd drive pins can be switched to function as output ports. built-in 8-bit synchronous serial i/o circuit one 8-bit programmable timer (that can be used as an event counter) one 8-bit programmable reload timer (that can be used to generate a remote control carrier signal) the whole ram area can be used as working area (by using the ram bank register) built-in ram data pointer built-in clock oscillator and 15-bit divider (also used to generate the lcd alternating frequency) highly flexible lcd panel drive output pins (35 pins) lcd panel ................number of ...........required drive type...................segments ..............common pins 1/3 bias 1/4 duty ........140 segments .......four pins 1/3 bias 1/3 duty ........105 segments .......three pins 1/2 bias 1/4 duty ........140 segments .......four pins 1/2 bias 1/3 duty ........105 segments .......three pins 1/2 bias 1/2 duty ........70 segments .........two pins static..........................35 segments .........one pin the lcd output pins can be switched to function as general-purpose outputs. c-mos type: up to 35 pins p-channel type: up to 35 pins n-channel type: up to 35 pins these microprocessors allow the use of an oscillator appropriate to the application system specifications. crystal oscillator: 32 khz, 65 khz or 38 khz (for the time base, system clock or lcd alternating frequency) ceramic oscillator: 400 khz to 4 mhz (for the system clock and the timers and serial counter) rc oscillator: 200 khz to 1 mhz (for the system clock and the timers and serial counter) external clock (for the system clock and the timers and serial counter) preliminary lc587008, 587006, 587004 sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan single-chip 4-bit microprocessors with lcd driver, 2 kb ram, and 8, 12, or 16 kb rom on chip cmos lsi
features these microprocessors are the top end of the lc5870 series and have the following features. faster cycle times cycle time: 2 s for v dd between 4.5 and 6.0 v cycle time: 10 s for v dd between 2.2 and 6.0 v low power dissipation halt mode (typical) continuous operation (typical) ceramic filter (cf) 4 mhz (5.0 v) 600 a 1.7 ma (cycle time = 2 s) crystal oscillator 32 khz (3.0 v, cf stopped) 4.0 a 20 a (cycle time = 122 s) improved timer functions one 8-bit programmable timer (that can be used as an event counter) one 8-bit programmable reload timer (that can be used to generate a remote control carrier signal) time base timer (for use as a clock) watchdog timer improved standby functions clock standby function (halt mode), software switching between low speed mode (low current) and high speed mode full standby mode (hold mode) halt and hold modes can be cleared by external interrupt pins, input ports (up to nine pins) and serial i/o interrupts improved i/o functions external interrupt pins up to 9 input and i/o pins that can clear halt and hold modes up to 24 input ports with built-in software controllable input resistors (either pull-up or pull- down specified as mask options) up to 25 input port pins with a built-in floating prevention circuit lcd driver: four common pins and 35 segment pins general-purpose i/o ports: 20 pins (of which 12 are p-channel open drain and 4 are n-channel open drain) general-purpose inputs: five pins general-purpose outputs (type 1): four pins (led direct drive pins, one internal alarm signal output pin and one carrier output pin) general-purpose outputs (type 2): 35 pins (when all 35 lcd segment port pins are switched over to function as general-purpose outputs) eight-bit serial i/o port: one set (three pins: input, output and clock) delivery formats: qfp80 (qip80) and chip p ac ka g e dimensions unit: mm 3044b-qfp80a no. 4435- 2 /29 lc587008, 587006, 587004 sanyo: qip80a [lc587008, 587006, 587004]
pad layout chip size: 5.12 mm 5.29 mm pad size: 120 m 120 m chip thickness: 480 m (chip products) pin assignments/pad names and coordinates note: 1. pin numbers are for qip80 package products. 2. connect the test pins (tst) to v ss . 3. pad numbers 40 and 41 must be left open in the chip specification product. 4. do not use dip-soldering techniques to mount the qip80 package versions. 5. for chip products either connect the substrate to v ss or leave it open. no. 4435- 3 /29 lc587008, 587006, 587004 pin pad symbol coordinates no. no. x m y m 24 1 v dd 2234 ?319 25 2 cfin 2234 ?883 26 3 cfout 2234 ?701 27 4 s1 2234 ?458 28 5 s2 input 2234 ?212 29 6 s3 port 2234 ?15 30 7 s4 2234 ?69 31 8 k1 2234 ?84 32 9 k2 i/o port 2234 ?01 33 10 k3 2234 81 34 11 k4 2234 264 35 12 m1 2234 448 36 13 m2 i/o port 2234 631 37 14 m3 2234 814 38 15 m4 2234 997 39 16 n1 2234 1352 40 17 n2 output 2234 1624 41 18 n3 port 2234 1895 42 19 n4 2234 2173 43 20 tst 1958 2449 44 21 seg 1 1732 2449 45 22 seg 2 1506 2449 46 23 seg 3 1280 2449 47 24 seg 4 1054 2449 48 25 seg 5 874 2449 49 26 seg 6 694 2449 50 27 seg 7 514 2449 51 28 seg 8 335 2449 pin pad symbol coordinates no. no. x m y m 52 29 seg 9 155 2449 53 30 seg 10 ?4 2449 54 31 seg 11 ?04 2449 55 32 seg 12 ?84 2449 56 33 seg 13 ?64 2449 57 34 seg 14 ?44 2449 58 35 seg 15 ?23 2449 59 36 seg 16 ?103 2449 60 37 seg 17 ?283 2449 61 38 seg 18 ?463 2449 62 39 seg 19 ?643 2449 40 test ?821 2449 41 test ?001 2449 63 42 seg 20 ?362 2449 64 43 seg 21 ?362 2248 65 44 seg 22 ?362 1649 66 45 seg 23 ?362 1468 67 46 seg 24 ?362 1288 68 47 seg 25 ?362 1107 69 48 seg 26 ?362 799 70 49 seg 27 ?362 618 71 50 seg 28 ?362 438 72 51 seg 29 ?362 257 73 52 seg 30 ?362 77 74 53 seg 31 ?362 ?03 75 54 seg 32 ?362 ?83 76 55 seg 33 ?362 ?64 77 56 seg 34 ?362 ?64 pin pad symbol coordinates no. no. x m y m 78 57 seg 35 ?362 ?24 79 58 com4 ?362 ?139 80 59 com3 ?362 ?564 1 60 com2 ?362 ?319 2 61 com1 ?912 ?319 3 62 cup1 ?730 ?319 4 63 cup2 ?549 ?319 5 64 res ?327 ?319 6 65 int ?145 ?319 7 66 so1 ?63 ?319 8 67 so2 i/o port, ?80 ?319 9 68 so3 sio port ?97 ?319 10 69 so4 ?14 ?319 11 70 a1 ?31 ?319 12 71 a2 i/o port ?8 ?319 13 72 a3 134 ?319 14 73 a4 317 ?319 15 74 p1 504 ?319 16 75 p2 i/o port 687 ?319 17 76 p3 870 ?319 18 77 p4 1053 ?319 19 78 xtout 1279 ?319 20 79 xtin 1462 ?319 21 80 v dd 2 1685 ?319 22 81 v dd 1 1868 ?319 23 82 v ss 2050 ?319
system block diagram system block diagram for the lc587008, LC587006 and lc587004 ram: data memory rom: program memory dp: data pointer register bnk: bank register apg: ram page flags ac: accumulator alu: arithmetic and logic unit b: b register opg: rom page flag pc: program counter ir: instruction register sts1: status register 1 sts2: status register 2 sts3: status register 3 sts4: status register 4 sts5: status register 5 pla: segment data and strobe programmable logic array wait.c: waiting time counter no. 4435- 4 /29 lc587008, 587006, 587004
pin functions no. 4435- 5 /29 lc587008, 587006, 587004 pin i/o qip-80 function option at reset pin no. v dd 24 v ss 23 v dd 1 22 v dd 2 21 cup1 3 cup2 4 cfin input 25 cfout output 26 xtin input 20 xtout output 19 s1 27 s2 28 s3 input 29 s4 30 k1 31 k2 32 k3 i/o 33 k4 34 m1 35 m2 i/o 36 m3 37 m4 38 a1 11 a2 i/o 12 a3 13 a4 14 p1 15 p2 i/o 16 p3 17 p4 18 power supply lcd drive power supply switching pin used to supply the lcd drive voltage to the v dd 1 and v dd 2 pins connect a nonpolarized capacitor between cup1 and cup2 when 1/2 or 1/3 bias is used. leave open when a bias other than 1/2 or 1/3 is used. cf specifications rc specifications external specifications not used the pull-up or pull- down resistors are on. note: these pins go to the floating state when reset is cleared. the pull-up or pull- down resistors are on. note: these pins go to the floating state when reset is cleared. input mode output latch data is set high. 32k specifications 65k specifications 38k specifications not used transistors to hold a low or high level selection of either pull-up or pull- down resistors transistors to hold a low or high level selection of either pull-up or pull- down resistors the same as k1 to k4 the same as k1 to k4 the same as k1 to k4 the same as k1 to k4 the same as k1 to k4 the same as k1 to k4 system clock oscillator connections ceramic resonator connection (cf specifications) rc component connection (rc specifications) external signal input pin (cfout is left open) this oscillator is stopped by the execution of a stop or slow instruction. reference calculation (clock specifications, lcd alternating frequency), system clock oscillator 32 khz crystal resonator connection 65 khz crystal resonator connection this oscillator is stopped by the execution of a stop instruction. input-only ports input pins used to read data into ram built-in 7.8 ms and 1.95 ms chatter rejection circuits built-in pull-up/pull-down resistors note: the 7.8 ms and 1.95 ms times are the times when ? is 32.768 khz. i/o ports input pins used to read data into ram output pins used to output data from ram built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits. the selection of 7.8 or 1.95 ms is linked to that for the s ports. note: the 7.8 ms and 1.95 ms times are the times when ? is 32.768 khz. i/o ports input pins used to read data into ram output pins used to output data from ram m4 is used as the external clock input pin in tm2 mode 3. * the minimum period for the external clock is twice the cycle time. built-in pull-up/pull-down resistors i/o ports input pins used to read data into ram output pins used to output data from ram built-in pull-up/pull-down resistors i/o ports function: the same as pins a1 to a4 continued on next page.
continued from preceding page. no. 4435- 6 /29 lc587008, 587006, 587004 continued on next page. pin i/o qip-80 function option at reset pin no. so1 7 so2 i/o 8 so3 9 so4 10 n1 39 n2 output 40 n3 41 n4 42 int input 6 res input 5 tst input 43 i/o ports function: the same as for pins a1 to a4 pins so1 to so3 area also used for the serial interface. use of these pins in serial mode can be selected under program control. pin functions: so1: serial input pin so2: serial output pin so3: serial clock pin the serial clock pin can be switched between internal and external, and between rising edge output and falling edge output. transistors to hold a low or high level selection of either pull-up or pull- down resistors internal serial clock divisor selection i 1/1 ii 1/2 iii 1/4 the same as for k1 to k4 the output levels on pins n1 to n4 can be specified as an option. pins n1 to n4 output circuit type: i cmos ii n-channel open drain pins n1 to n4 output level i high level ii low level transistors to hold a low or high level selection of either pull-up or pull- down resistors signal conversion (rising/falling) selection * only when the input resistor open specification is selected lcd driver/ general-purpose output switching lcd drive type switching static 1/2 bias ?1/2 duty 1/2 bias ?1/3 duty 1/2 bias ?1/4 duty 1/3 bias ?1/3 duty 1/3 bias ?1/4 duty general-purpose output circuit switching cmos p-channel open drain n-channel open drain output latch control in standby modes lcd drive all segments on all segments off * : determined by mask options general purpose outputs high level low level * : determined by mask options note: when a combination of lcd drive and general- purpose outputs, the output state is either: all lit/high level all off/low level. these pins go to the static drive mode during the reset period. output-only ports output pins used to output data from ram an alarm signal can be output from pin n4. (note that this is only when the n4 output latch is low.) an alarm signal modulated at 1, 2 or 4 khz can be output. (these frequencies are output when ? is 32.768 khz.) a carrier signal can be output from n3. (note that this is only when the n3 output latch is low.) input ports external interrupt request inputs input pins used to read data into ram input detection can be performed on either rising or falling edges. built-in pull-up/pull-down resistors lsi internal reset input the reset input level can be selected to be either high or low. built-in pull-up/pull-down resistors note: the reset pulse must be at least 500 s. test input qip80 products: connect to v ss . chip products: leave open or connect to v ss . lcd panel drive/general-purpose output lcd panel drive i static ii 1/2 bias ?1/2 duty iii 1/2 bias ?1/3 duty iv 1/2 bias ?1/4 duty v 1/3 bias ?1/3 duty vi 1/3 bias ?1/4 duty types i to v can be specified as mask options. general-purpose output mode i cmos ii p-channel open drain iii n-channel open drain types i to iii can be specified as mask options. lcd/general-purpose output control is handled by the segment pla, and thus program control is not required. these pins support output latch control on reset and in standby states when the oscillators are stopped. arbitrary combinations of lcd drive and general-purpose outputs can be used. seg1, seg2 to seg35 output 44, 45 to 78
continued from preceding page. sample application circuit lcd: 1/2 bias ?1/4 duty no. 4435- 7 /29 lc587008, 587006, 587004 pin i/o qip-80 function option at reset pin no. com1 2 com2 1 com3 output 80 com4 79 the static drive waveform is output during the reset period. * there are cases where the alternating frequency stops for the cf, rc and external clock specifications. (these cases differ depending on option specifications.) lcd panel drive common polarity outputs the table below shows how these pins are used depending on the duty used. (values for alternating frequency reflect a typical specification of 32.768 mhz for ?.) note: a cross ( 5 ) indicates that the pin is not used with that duty type. static duty 1/2 duty 1/3 duty 1/4 duty com1 o o o o com2 5 o o o com3 5 5 o o com4 5 5 5 o alternation 32 hz 32 hz 42.7 hz 32 hz frequency
oscillator circuit options no. 4435- 8 /29 lc587008, 587006, 587004 option circuit configuration note rc and xtal cf and xtal 400 khz (cf) 4 mhz (cf) rc the cycle time is four times the f1 period. the divider outputs (? to ?5) are used as the time base, the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. osc1 is stopped when a slow instruction is executed. the cycle time is four times n times the f1 period. (note: n is 2.) the divider outputs (? to ?5) are used as the time base, the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. osc1 is stopped when a slow instruction is executed. the cycle time is four times the f1 period. the divider outputs (? to ?5) are used as the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. continued on next page.
continued from preceding page. no. 4435- 9 /29 lc587008, 587006, 587004 option circuit configuration note cf 400 khz 4 mhz xtal external input the cycle time is four times n times the f1 period. (note: n is 2.) the divider outputs (? to ?5) are used as the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. the cycle time is four times the f2 period. the divider outputs (? to ?5) are used as the time base, the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. the cycle time is four times n times the f1 period. (note: n is 2.) the divider outputs (? to ?5) are used as the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions.
crystal oscillator circuit options input port options no. 4435- 10 /29 lc587008, 587006, 587004 option circuit configuration note 32 khz oscillator 5 khz oscillator 38 khz oscillator the resistor rd (200 k typical) for use with a 32 khz oscillator is built in. the cycle time is four times n times the f1 period. (note: n is 2.) the divider outputs (? to ?5) are used as the time base, the lcd drive waveform generation clock, the s and k port chattering rejection clock and for other functions. osc1 is stopped when a slow instruction is executed. option circuit configuration note selection of either the built-in pull-up resistor, or the built-in pull-down resistor option selection of high or low level hold transistor the following ports are switched at the same time s1 to s4, k1 to k4, m1 to m4, p1 to p4 so1 to so4 and a1 to a4 at reset: the resistors are on during the reset period. the resistors are turned off when reset is cleared. options: either a or b can be selected. one of a and b must be selected. when the hold transistors used option is selected: used to reduce the current flowing in the pull-up or pull-down resistors when, for example, a push switch is used for s1 or a slide switch is used for s2. for input open specification versions, the resistors are turned on before the input is read, the input state is read and then the resistors are turned off. if the input is floating at this point the high or low level hold transistor operates to hold the value read. when the hold transistors unused option is selected: use with the pull-up or pull-down resistor in the on state. select hold transistors unused when connecting to external control signals and the connections will never be floating combination examples type 1 2 3 4 pull-up resistor (a) on on pull-down resistor (b) on on high level hold transistor (c) on low level hold transistor (d) on
int pins res pin pins n1 to n4 no. 4435- 11 /29 lc587008, 587006, 587004 option circuit configuration note pull-up resistor, pull- down resistor or resistor open selection high or low level hold transistor selection rising edge or falling edge detection selection built-in resistor selection pull-up resistor used pull-down resistor used used open input signal level hold transistor selection high level hold transistor used low level hold transistor used level hold transistors unused signal change edge detection switching change on rising signal change on falling signal option circuit configuration note pull-up resistor, pull- down resistor or resistor open and reset level selection built-in resistor and polarity selection pull-up resistor connected, low level reset pull-down resistor connected, high level reset resistors open, low level reset resistors open, high level reset option circuit configuration note n-channel/cmos selection selection of cmos or n-channel open drain circuit type pins n1 to n4 can be specified independently the output level during reset can be specified. ?high level ?low level
fifteen-stage divider overflow time k input port options no. 4435- 12 /29 lc587008, 587006, 587004 option circuit configuration note 1000 ms/250 ms 500 ms/125 ms a 15-stage (15-bit) divider is provided on chip to count the reference time. one of two types of divider overflow detection can be selected as a mask option and a further selection of two types can be made under program control. one of these mask options must be specified. option circuit configuration note pull-up/pull-down resistor selection when the pull-up/pull-down resistor selection is made, the k port input detection switching gate is switched accordingly. a: when all of k1 to k4 are high and even one pin goes low a signal is applied to the edge detection circuit. (applies to the pull- up specifications.) note: when even one of the k1 to k4 pins is low, the edge detection circuit will not operate for any combination of high or low values on the other pins. b: the opposite of item a
mask option overview 1. port resistor selection (ports s, k, p, m, a and so) pull-up resistor specification pull-down resistor specification 2. s port high or low level hold transistors level hold transistors used no level hold transistors 3. k port high or low level hold transistors level hold transistors used no level hold transistors 4. m port high or low level hold transistors level hold transistors used no level hold transistors 5. p port high or low level hold transistors level hold transistors used no level hold transistors 6. a port high or low level hold transistors level hold transistors used no level hold transistors 7. so port high or low level hold transistors level hold transistors used no level hold transistors 8. int pin resistor selection and signal edge selection pull-up resistor (negative edge) pull-down resistor (positive edge) open (negative edge) open (positive edge) 9. int pin level hold transistor selection low or high level hold transistors used no low or high level hold transistors 10. res pin pull-up resistor (low level reset) pull-down resistor (high level reset) open (low level reset) open (high level reset) 11. n1 pin n-channel open drain type cmos type 12. n2 pin n-channel open drain type cmos type 13. n3 pin n-channel open drain type cmos type no. 4435- 13 /29 lc587008, 587006, 587004
14. n4 pin n-channel open drain type cmos type 15. n port initial level high level low level 16. osc specifications cf only (ceramic filter) rc only (resistor and capacitor oscillator) crystal only (32 to 65 khz crystal oscillator) cf + crystal rc + crystal external + crystal 17. cf/external 400 khz or 800 khz 1 mhz, 2 mhz or 4 mhz 18. crystal oscillator 32 khz 65 khz 38 khz 19. fifteen-bit counter overflow ?/2048 or ?8192 ?/4096 or ?/16384 20. serial i/o internal clock period cycle time 1 2 cycle time 2 2 cycle time 4 2 21. lcd driver static 1/2 bias ?1/2 duty 1/2 bias ?1/3 duty 1/2 bias ?1/4 duty 1/3 bias ?1/3 duty 1/3 bias ?1/4 duty 22. lcd alternating frequency slow typical fast 23. internal reset circuit selection disabled 24. segment ports at reset lcd drive pins all on all off cmos, p/n-channel type pins high level no. 4435- 14 /29 lc587008, 587006, 587004
internal register functions no. 4435- 15 /29 lc587008, 587006, 587004 symbol r/w function initialization value at reset pc rom ram r/o r/w program counter the pc is a 13-bit counter that indicates the address in program memory (rom) of the next instruction to execute. normally the pc is incremented on every instruction cycle in the range 000h to 1f7fh. (addresses in the range 1f80 to 1fff are reserved for testing and cannot be used by user programs.) however, data values are loaded into the pc by the execution of branch and subroutine instructions and on the occurrence of interrupts or an initial reset. the table below describes the data loaded for these operations. page: the rom page flags, which take 2048 locations as a single page the page is specified with the mropf and sropf instructions. p00 to p10: bits in the instruction code (i.e., immediate data) program memory the rom memory consists of 4096 x 16 bits (4 kwords or 8 kbytes) in the lc587004, 6144 x 16 bits (6 kwords or 12 kbytes) in the LC587006 and 8064 x 16 bits (8 kwords or 16 kbytes) in the lc587008. rom hold user programs to be executed. data memory these microprocessors provide an on-chip ram that consists of 512 4 bits (2 kb). this ram is accessed as two 256 4-bit pages. ram addresses can be specified in four ways as listed below. directly specified at 00h to ffh (immediate addressing) indirect specification using the 8-bit data pointer. indirect specification by the 4-bit ram bank register multiplied by 10h plus immediate data in the range 0 to fh. indirect specification by the 4-bit ram bank register multiplied by 10h plus 8h plus immediate data in the range 0 to fh. writing to ram is always performed through the accumulator. pc pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 operation initializing reset 0 0 0 0 0 0 0 0 0 0 0 0 0 int pin external interrupt 0 0 0 0 0 0 0 1 0 0 0 0 0 s/k pin external interrupt 0 0 0 0 0 0 0 1 0 1 0 0 0 timer 1 or timer 2 internal 0 0 0 0 0 0 0 1 1 0 0 0 0 interrupt serial counter internal interrupt 0 0 0 0 0 0 0 1 1 1 0 0 0 or so4 pin external interrupt unconditional jump (jmp) page p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 conditional jump (bab0, bab1, bab2, bab3, page p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 baz, banz, bch, bcnh) call instruction (call) page p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 return instruction (rts, rtsr) call address + 1 undefined continued on next page.
continued from preceding page. no. 4435- 16 /29 lc587008, 587006, 587004 symbol r/w function initialization value at reset ram ac b dp r/w r/w r/w r/w note: in case b, data pointer ram address specification is illegal if the ram address specification (the dph immediate data) has the same value as the ram bank register (bnk). in this case immediate specification is allowed. example: if an ips 10h instruction is executed when the data pointer flag is set, dph is 5h, dpl is 3 h and the ram bank register (bnk) is 1h, then the contents of the s port will be written to ram location 10h. example: if bnk and dph differ, then the following operation will be performed. if an ips 10h instruction is executed when dpf is 1, dph is 5, dpl is 3 and bnk is 4, then the contents of the s port will be written to ram location 53h. accumulator b register this register is used in combination with ram as a pair for output to the lcd ports and for timer 2, serial counter and data pointer i/o. data pointer the data pointer register functions as a data pointer when the data pointer flag (dpf) is set, allowing control of the on- chip ram. undefined undefined undefined undefined continued on next page.
continued from preceding page. no. 4435- 17 /29 lc587008, 587006, 587004 symbol r/w function initialization value at reset stack bnk apg tim tim1 tim2 r/w r/w r/w r/w stack pointer the stack consists of eight 14-bit registers and thus can be set to a depth of up to eight levels. the stack pointer is incremented by call instructions and interrupts, and decremented by rts, rtsr and pop instructions. p0 to p11: program counter (pc) dpf: data pointer flag bank register the bank register is a 4-bit register that divides ram (from 00h to ffh) into 16 sections and is used in moving ram data, immediate operations and setting the data pointer. example: add * _5,10.....if bnk is 6 then the operation performed will be: ram(65h) + 10 ? ac ? ram(65h). ram page flags the ram page flags consist of 2 bits that allow ram to be expanded in 256 4-bit pages to a total of 1024 4-bit locations. note: pages 2 and 3 cannot be used by the lc587004, LC587006 and lc587008. timer counters the timers consist of 8-bit down counters. (timer 1 and timer 2) timer setting is performed in 8-bit units for immediate data. (timer 1 and timer 2) reading and writing the lower 4 bits of a timer counter is performed through a ram location. (timer 2 only) reading and writing the upper 4 bits of a timer counter is performed using the b register. (timer 2 only) 01h 00h 00h undefined continued on next page.
continued from preceding page. no. 4435- 18 /29 lc587008, 587006, 587004 symbol r/w function initialization value at reset sio opg sts1 sts2 r/w r/w r/o r/w serial counter the serial counter is an 8-bit shift register. reading and writing the lower 4 bits of the serial counter is performed through a ram location. reading and writing the upper 4 bits of the serial counter is performed using the b register. rom page flags the rom page flags consist of 2 bits that allow rom to be expanded in 2048 16-bit pages to a total of 8063 16-bit locations. in the lc587004 the legal values are 0 and 1, in the LC587006 the legal values are 0 to 2 and in the lc587008 the legal values are 0 to 3. (the operation when an illegal value is used is undefined.) status register 1 (sts1) status register 1 is a 4-bit register whose bits are used as shown below. status register 2 (sts2) status register 2 is a 4-bit register that is used for serial counter control and state confirmation. icf: high when the internal clock is used oself: high when the so2 pin is set to the high impedance state (z). low when so2 is set to the cmos or n-channel open drain state. siof: high when used as serial i/o cstf: high on serial counter start low during serial counter operation undefined 00h 00h 00h continued on next page.
continued from preceding page. no. 4435- 19 /29 lc587008, 587006, 587004 symbol r/w function initialization value at reset sts3 sts4 sts5 r/o r/o r/o status register 3 (sts3) status register 3 is a 4-bit register that is used to confirm the halt and stop clear conditions. scf0: set to 1 if there was a signal change on the int pin. scf1: set to 1 if there was a signal change on the k port. scf2: set to 1 if any of the flags in sts4 is set. scf3: set to 1 if there was a signal change on the s port. note: scf0 is used when enabled by an sf2-1 instruction. scf1 and scf3 are used when enabled by an ssw instruction. status register 4 (sts4) status register 4 is a 4-bit register that is used to confirm the halt and stop clear conditions. scf4: divider overflow scf5: timer 1 underflow scf6: timer 2 underflow scf7: serial counter overflow or signal change on so4 status register 5 (sts5) status register 5 is a 4-bit register whose bits are used as shown below. bits 0 and 1: these bits are always 0 and cannot be used. intin: reflects in the input data on the int pin. stbf: strobe flag for the segment port (set to 1 for 00 to 0f and to 0 for 10 to 1e.) 00h 00h 00h
specifications the electrical characteristics specified here are provisional and subject to change. absolute maximum ratings at v ss = 0 v, ta = 25 c allowable operating ranges at v ss = 0 v, ta = ?0 to +70 c note: in the state where the cf/rc oscillator and/or the crystal oscillator are completely stopped and the internal circuits are comp letely stopped. no. 4435- 20 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit v dd ?.3 +7.0 v maximum supply voltage v dd 1 ?.3 v dd v v dd 2 ?.3 v dd v v i (1) allowed in the specified circuit (figure 1), xtin, cfin allowed up to the generated voltage maximum input voltage v i (2) s1 to s4, k1 to k4, p1 to p4, so1 to so4, a1to a4,res, ?.3 v dd + 0.3 v int, tst, (with the k, p, m, so and ports in input mode) v o (1) allowed in the specified circuit (figure 1), xtout, allowed up to the generated voltage cfout maximum output voltage k1 to k4, p1 to p4, so1 to so4, a1 to a4, n1 to n4, v o (2) cup1, cup2, seg1 to seg35, com1 to com4 ?.3 v dd + 0.3 v (with the k, p, m, so and a ports in output mode) v o (3) open drain specifications, n1 to n4 (n ch) ?.3 +13 v i o (1) n1 to n4 0 +15 ma i o (2) per pin ?0 0 ma output pin current i o (3) k1 to k4, p1 to p4, m1 to m4, so1 to so4, 0 5 ma i o (4) a1 to a4 ? 0 ma s i o (1) total current k1 to k4, p1 to p4, m1 to m4, so1 to 70 ma s i o (2) for all pins so4, a1 to a4, n1 to n4, seg1 to seg35 ?0 ma allowable power dissipation pd max qip80 flat package 500 mw operating temperature topg ?0 +70 c storage temperature tstg ?5 +125 c parameter symbol conditions min typ max unit lcd unused specifications: v dd 1 = v dd 2 = v dd 2.0 6.0 v supply voltage v dd static specifications: v dd 1 = v dd 2 = v dd 2.0 6.0 v 1/2 bias specifications: v dd 1 = v dd 2 2 1/2 v dd 2.8 6.0 v 1/3 bias specifications: v dd 1 2 1/3 v dd , 2.8 6.0 v v dd 2 1/3 v dd hold supply voltage v hd voltage required to hold the contents of ram and 2.0 v dd v the registers * input high level voltage v ih 1 0.7 v dd v dd v input low level voltage v il 1 0 0.3 v dd v input high level voltage v ih 2 res pin 0.75 v dd v dd v input low level voltage v il 2 0 0.25 v dd v input high level voltage v ih 3 cfin pin 0.75 v dd v dd v input low level voltage v il 3 0 0.25 v dd v operating frequency 1 fopg1 v dd = 2.0 to 6.0 v, 32 khz xtin/xtout crystal 32 33 khz operating frequency 2 fopg2 v dd = 2.2 to 6.0 v. 38 khz oscillator 37 39 khz operating frequency 3 fopg3 v dd = 2.2 to 6.0 v, 65 khz 60 70 khz operating frequency 4 fopg4 v dd = 2.2 to 6.0 v 190 810 khz operating frequency 5 fopg5 v dd = 2.5 to 6.0 v cfin/cfout cf specifications 190 1200 khz operating frequency 6 fopg6 v dd = 2.5 to 6.0 v 190 2300 khz operating frequency 7 fopg7 v dd = 2.8 to 6.0 v 190 4200 khz operating frequency 8 fopg8 v dd = 4.0 to 6.0 v, cfin/cfout rc specifications 100 1500 khz operating frequency 9 fopg9 v dd = 2.0 to 6.0 v, cfin/cfout ext specifications 190 800 khz v dd = 3.0 to 6.0 v, o1/so3 pins (in serial mode), operating frequency 10 fopg10 rising and falling edges on the input signals and dc 200 khz clock waveform of the so1/so3 pins (in serial mode) must be 10 s or less. s1 to s4, k1 to k4, p1 to p4, m1 to m4, so1 to so4, a1 to a4, int, (with the k, p, m, so and ports in input mode)
electrical characteristics at v dd = 2.5 to 3.2 v, v ss = 0 v, ta = ?0 to +70 c note: for the 24 pins s1 to s4, k1 to k4, p1 to p4, m1 to m4, so1 to so4 and a1 to a4. no. 4435- 21 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit r in 1 a v in = 0.2 v dd , low level hold transistor * figure 2 60 300 1200 k r in 1 b v in = v dd , pull-down resistor * figure 2 30 150 500 k r in 1 c v in = 0.8 v dd , high level hold transistor * figure 2 60 300 1200 k r in 1 d v in = v ss , pull-up resistor * figure 2 30 150 500 k r in 2 a v in = 0.2 v dd , the int pin low level hold transistor 60 300 1200 k r in 2 b v in = v dd , the int pin pull-down resistor 300 1500 5000 k r in 2 c v in = 0.8 v dd , the int pin high level hold transistor 60 300 1200 k r in 2 d v in = v ss , the int pin pull-up resistor 300 1500 5000 k r in 3 v in = v dd , the res pin pull-down resistor 10 30 50 k r in 4 v in = v ss , the res pin pull-up resistor 10 30 50 k r in 5 v in = v dd , the tst pin pull-down resistor 60 250 1000 k r in 1 a v in = 0.2 v dd , low level hold transistor * 80 300 1200 k figure 2 input resistance r in 1 b v in = v dd , pull-down resistor * figure 2 40 150 500 k r in 1 c v in = 0.8 v dd , high level hold transistor * 80 300 1200 k figure 2 r in 1 d v in = v ss , pull-up resistor * figure 2 40 150 500 k r in 2 a v in = 0.2 v dd , the int pin low level hold 80 300 1200 k transistor v dd = 2.5 v r in 2 b v in = v dd , the int pin pull-down resistor 400 1500 5000 k r in 2 c v in = 0.8 v dd , the int pin high level hold 80 300 1200 k transistor r in 2 d v in = v ss , the int pin pull-up resistor 400 1500 5000 k r in 3 v in = v dd , the res pin pull-down resistor 10 30 50 k r in 4 v in = v ss , the res pin pull-up resistor 10 30 50 k r in 5 v in = v dd , the tst pin pull-down resistor 80 250 1000 k output high level voltage v oh (1) i oh = ?00 a n1 to n4 v dd ?0.5 v output low level voltage v ol (1) i ol = 1.0 ma 0.5 v output high level voltage v oh (2) i oh = ?00 a k1 to k4, p1 to p4, m1 to m4, so1 to v dd ?0.5 v so4, a1 to a4 (with the k, p, m, so output low level voltage v ol (2) i ol = 400 a and a ports in output mode) 0.5 v output off leakage current ? i off ? v oh = 10.5 v n1 to 4 (open specifications), figure 10 1.0 a segment port output impedances [in cmos output port mode] output high level voltage v oh (3) i oh = ?00 a seg1 to seg35 v dd ?0.5 v output low level voltage v ol (3) i ol = 100 a 0.5 v [in p-channel open-drain output port mode (see figure 11.)] output high level voltage v oh (3) i oh = ?00 a seg1 to seg35 v dd ?0.5 v output off leakage current ? i off ? v ol = v ss 1.0 a [in n-channel open-drain output port mode (see figure 11.)] output low level voltage v ol (3) i ol = 100 a seg1 to seg35 0.5 v output off leakage current ? i off ? v oh = v dd 1.0 a [static drive] output high level voltage v oh (4) i oh = ?0 a, seg1 to seg35 v dd ?0.2 v output low level voltage v ol (4) i ol = 20 a 0.2 v output high level voltage v oh (5) i oh = ?00 a, com1 v dd ?0.2 v output low level voltage v ol (5) i ol = 100 a 0.2 v
electrical characteristics at v dd = 3.0 to 4.5 v, v ss = 0 v, ta = ?0 to +70 c note: for the 24 pins s1 to s4, k1 to k4, p1 to p4, m1 to m4, so1 to so4 and a1 to a4. no. 4435- 22 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit r in 1 a v in = 0.2 v dd , low level hold transistor * figure 2 35 200 800 k r in 1 b v in = v dd , pull-down resistor * figure 2 15 80 300 k r in 1 c v in = 0.8 v dd , high level hold transistor * figure 2 35 200 800 k r in 1 d v in = v ss , pull-up resistor * figure 2 15 80 300 k r in 2 a v in = 0.2 v dd , the int pin low level hold transistor 35 200 800 k r in 2 b v in = v dd , the int pin pull-down resistor 150 800 3000 k r in 2 c v in = 0.8 v dd , the int pin high level hold transistor 35 200 800 k r in 2 d v in = v ss , the int pin pull-up resistor 150 800 3000 k r in 3 v in = v dd , the res pin pull-down resistor 10 30 50 k r in 4 v in = v ss , the res pin pull-up resistor 10 30 50 k r in 5 v in = v dd , the tst pin pull-down resistor 25 130 500 k r in 1 a v in = 0.2 v dd , low level hold transistor * 40 200 800 k figure 2 input resistance r in 1 b v in = v dd , pull-down resistor * figure 2 20 80 300 k r in 1 c v in = 0.8 v dd , high level hold transistor * 40 200 800 k figure 2 r in 1 d v in = v ss , pull-up resistor * figure 2 20 80 300 k r in 2 a v in = 0.2 v dd , the int pin low level hold v dd = 40 300 800 k transistor 3.0 to 4.0 v r in 2 b v in = v dd , the int pin pull-down resistor 200 800 3000 k r in 2 c v in = 0.8 v dd , the int pin high level hold 40 200 1200 k transistor r in 2 d v in = v ss , the int pin pull-up resistor 200 800 3000 k r in 3 v in = v dd , the res pin pull-down resistor 10 30 50 k r in 4 v in = v ss , the res pin pull-up resistor 10 30 50 k r in 5 v in = v dd , the tst pin pull-down resistor 30 130 500 k output high level voltage v oh (1) i oh = ?00 a n1 to n4 v dd ?0.5 v output low level voltage v ol (1) i ol = 1.0 ma 0.5 v output high level voltage v oh (2) i oh = ?00 a k1 to k4, p1 to p4, m1 to m4, so1 to v dd ?0.5 v so4, a1 to a4 (with the k, p, m, so output low level voltage v ol (2) i ol = 400 a and a ports in output mode) 0.5 v output off leakage current ? i off ? v oh = 10.5 v n1 to 4 (open specifications), figure 10 1.0 a segment port output impedances [in cmos output port mode] output high level voltage v oh (3) i oh = ?00 a seg1 to seg35 v dd ?0.5 v output low level voltage v ol (3) i ol = 100 a 0.5 v [in p-channel open-drain output port mode (see figure 11.)] output high level voltage v oh (3) i oh = ?00 a seg1 to seg35 v dd ?0.5 v output off leakage current ? i off ? v ol = v ss 1.0 a [in n-channel open-drain output port mode (see figure 11.)] output low level voltage v ol (3) i ol = 100 a seg1 to seg35 0.5 v output off leakage current ? i off ? v oh = v dd 1.0 a [static drive] output high level voltage v oh (4) i oh = ?0 a, seg1 to seg35 v dd ?0.2 v output low level voltage v ol (4) i ol = 20 a 0.2 v output high level voltage v oh (5) i oh = ?00 a, com1 v dd ?0.2 v output low level voltage v ol (5) i ol = 100 a 0.2 v [1/2 bias drive] output high level voltage v oh (4) i oh = ?0 a seg1 to seg35 v dd ?0.2 0.2 v output low level voltage v ol (4) i ol = 20 a output high level voltage v oh (5) i oh = ?00 a v dd ?0.2 v output middle level voltage v om i oh = ?00 a com1 to com4 v dd /2 ?0.2 v dd /2 + 0.2 v i ol = 100 a output low level voltage v ol (5) i ol = 100 a 0.2 v continued on next page.
continued from preceding page. no. 4435- 23 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit [1/3 bias drive: about 1/10 of the rating for v dd = 4.5 to 6.0 v] supply leakage current i lek (1) v dd = 3.0 v, ta = 25 c, figure 3 0.2 1.0 a supply leakage current i lek (2) v dd = 3.0 v, ta = 50 c, figure 3 1.0 5.0 a v dd = 3.0 v input leakage current i off v in = v dd 1.0 a v in = v ss ?.0 a output voltage 1 v dd 1-(1) v dd = 3.0 v, c1 = c2 = 0.1 f, v dd 1 = v o , 1.3 1.5 1.7 v 1/2 bias, fopg = 32.768 khz, figure 4 ? i dd ? 1-1 v dd = 3.0 v, 4.0 8.0 a supply current 1 ta = 25 c ? i dd ? 1-2 v dd = 3.0 v, 20 a ta = 50 c ? i dd ? 2-1 v dd = 3.0 v, 6.0 10 v supply current 2 ta = 25 c ? i dd ? 2-2 v dd = 3.0 v, 30 a ta = 50 c ? i dd ? 3-1 v dd = 3.0 v, 150 300 a supply current 3 ta = 25 c ? i dd ? 3-2 v dd = 3.0 v, 500 a ta = 50 c oscillator start voltage ? v stt ? t stt 5 s 2.2 v oscillator hold voltage ? v hold ? 2.0 6.0 v oscillator start time ? t stt ? v dd = 2.2 v 5 s oscillator stability ? f v dd = 2.95 to 3 ppm 3.05 v oscillator start voltage ? v stt ? t stt 5 s 2.4 v oscillator hold voltage ? v hold ? 2.2 6.0 v oscillator start time ? t stt ? v dd = 2.4 v 5 s oscillator start voltage ? v stt ? t stt 30 ms 2.4 v oscillator hold voltage ? v hold ? 2.2 6.0 v oscillator start time ? t stt ? v dd = 2.4 v 30 ms oscillator start voltage ? v stt ? t stt 30 ms 2.4 v oscillator hold voltage ? v hold ? 2.2 6.0 v oscillator start time ? t stt ? v dd = 2.4 v 30 ms oscillator correction capacitance cd v dd = 3.0 v, xtout pin (built-in) 16 20 24 pf cf oscillator specifications, using an 800 khz ceramic filter, ccg = ccd = 220 pf or 100 pf, figure 7 cf oscillator specifications, using a 400 khz ceramic filter, ccg = ccd = 330 pf, figure 7 crystal oscillator specifications, using a 38 or 65 khz crystal, xcg = 10 pf, ci 25 k , figure 6 crystal oscillator specifications, using a 32 khz crystal, cg = 20 pf, ci 25 k , figure 6 cf oscillator specifications, cf: 400 khz, ccg = ccd = 330 pf, halt mode, figure 7 crystal oscillator specifications, crystal: 38 or 65 khz, cg = 10 pf, ci = 25 k , halt mode, figure 6, lcd = 1/3 bias crystal oscillator specifications, crystal: 32 khz, cg = 20 pf, ci = 25 k , halt mode, figure 6, lcd = 1/3 bias s1 to s4, k1 to k4, p1 to p4, m1 to m4, so1 to so4, a1 to a4, int, res (with the k, p, m, so and a ports in input mode, and with open specifications for the int and res pins)
electrical characteristics at v dd = 4.5 to 6.0 v, v ss = 0 v, ta = ?0 to +70 c note: for the 24 pins s1 to s4, k1 to k4, p1 to p4, m1 to m4, so1 to so4 and a1 to a4. no. 4435- 24 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit r in 1 a v in = 0.2 v dd , low level hold transistor * figure 2 30 120 500 k r in 1 b v in = v dd , pull-down resistor * figure 2 10 50 200 k r in 1 c v in = 0.8 v dd , high level hold transistor * figure 2 30 120 500 k r in 1 d v in = v ss , pull-up resistor * figure 2 10 50 200 k r in 2 a v in = 0.2 v dd , the int pin low level hold transistor 30 120 500 k input resistance r in 2 b v in = v dd , the int pin pull-down resistor 100 500 2000 k r in 2 c v in = 0.8 v dd , the int pin high level hold transistor 30 120 500 k r in 2 d v in = v ss , the int pin pull-up resistor 100 500 2000 k r in 3 v in = v dd , the res pin pull-down resistor 10 30 50 k r in 4 v in = v ss , the res pin pull-up resistor 10 30 50 k r in 5 v in = v dd , the tst pin pull-down resistor 20 70 300 k output high level voltage v oh (1) i oh = ?.0 ma n1 to n4 v dd ?0.5 v output low level voltage v ol (1) i ol = 10.0 ma 0.5 v output high level voltage v oh (2) i oh = ?.0 ma v dd ?0.5 v dd ?0.2 v output low level voltage v ol (2) i ol = 2.0 ma 0.2 0.5 v output off leakage current ? i off ? v oh = 10.5 v 1.0 a segment port output impedances [in cmos output port mode] output high level voltage v oh (3) i oh = ?00 a seg1 to seg35 v dd ?0.5 v dd ?0.2 v output low level voltage v ol (3) i ol = 500 a 0.5 v [in p-channel open-drain output port mode (see figure 11.)] output high level voltage v oh (4) i oh = ?00 a seg1 to seg35 v dd ?0.5 v dd ?0.2 v output off leakage current ? i off ? v ol = v ss 1.0 a [in n-channel open-drain output port mode (see figure 11.)] output low level voltage v ol (4) i ol = 500 a seg1 to seg35 0.2 0.5 v output off leakage current ? i off ? v oh = v dd 1.0 a [static drive] output high level voltage v oh (4) i oh = ?0 a seg1 to seg35 v dd ?0.2 v output low level voltage v ol (4) i ol = 40 a 0.2 v output high level voltage v oh (6) i oh = ?00 a com1 v dd ?0.2 v output low level voltage v ol (6) i ol = 400 a 0.2 v [1/2 bias drive] output high level voltage v oh (4) i oh = ?0 a seg1 to seg35 v dd ?0.2 v output low level voltage v ol (4) i ol = 40 a 0.2 v output high level voltage v oh (6) i oh = ?00 a v dd ?0.2 v output middle level voltage v om 2-1 i oh = ?00 a com1 to com4 v dd /2 ?0.2 v dd /2 + 0.2 v i ol = 400 a output low level voltage v ol (6) i ol = 400 a 0.2 v [1/3 bias drive] output high level voltage v oh (4) i oh = ?0 a v dd ?0.2 v v om 1-1 i oh = ?0 a 2 v dd /3 2 v dd /3 v output middle level voltage seg1 to seg35 ?0.2 + 0.2 v om 1-2 i ol = 40 a v dd /3 ?0.2 v dd /3 + 0.2 v output low level voltage v ol (4) i ol = 40 a 0.2 v output high level voltage v oh (6) i oh = ?00 a v dd ?0.2 v v om 2-1 i oh = ?00 a 2 v dd /3 2 v dd /3 v output middle level voltage com1 to com4 ?0.2 + 0.2 v om 2-2 i ol = 400 a v dd /3 ?0.2 v dd /3 + 0.2 v output low level voltage v ol (6) i ol = 400 a 0.2 v k1 to k4, p1 to p4, m1 to m4, so1 to so4, a1 to a4 (with the k, p, m, so and a ports in output mode), n1 to n4 (open specifications) figure 10 continued on next page.
continued from preceding page. no. 4435- 25 /29 lc587008, 587006, 587004 parameter symbol conditions min typ max unit i op -1 v dd = 3 v, ta = 25 c, 32 khz crystal oscillator, 20 30 a lcd = 1/3 bias, figure 6 i op -2 v dd = 5 v, ta = 25 c, 32 khz crystal oscillator, 40 60 a lcd = 1/3 bias, figure 6 operating current i op -3 v dd = 3 v, ta = 25 c, 400 khz, cf oscillator, figure 6 240 300 a i op -4 v dd = 5 v, ta = 25 c, 400 khz, cf oscillator, figure 6 620 780 a i op -5 v dd = 3 v, ta = 25 c, 1 mhz, cf oscillator, figure 6 350 480 a i op -6 v dd = 5 v, ta = 25 c, 1 mhz, cf oscillator, figure 6 850 1200 a i op -7 v dd = 5 v, ta = 25 c, 4 mhz, cf oscillator, figure 6 1700 2500 a supply leakage current i lek (1) v dd = 6.0 v, ta = 25 c, figure 3 0.2 1.0 a supply leakage current i lek (2) v dd = 6.0 v, ta = 50 c, figure 3 1.0 5.0 a v dd = 6.0 v a input leakage current i off v in = v dd 1.0 a v in = v ss ?.0 a output voltage 2 v dd 1-(2) v dd = 5.0 v, c1 = c2 = 0.1 f, figure 4, v dd 1 = v o 2.4 2.5 2.6 v 1/2 bias, fopg = 32.768 khz output voltage 3 v dd 1-(3) v dd = 5.0 v, c1 = c2 = 0.1 f, figure 4, v dd 1 = v o , 1.4 1.67 1.8 v v dd 2-(3) 1/3 bias, fopg = 32.768 khz v dd 2 = v o 3.1 3.33 3.5 v ? i dd ? 1-1 v dd = 5.0 v, 15 30 a supply current 1 ta = 25 c ? i dd ? 1-2 v dd = 5.0 v, 50 a ta = 50 c ? i dd ? 2-1 v dd = 5.0 v, 15 30 a supply current 2 ta = 25 c ? i dd ? 2-2 v dd = 5.0 v, 50 a ta = 50 c ? i dd ? 3-1 v dd = 5.0 v, 400 600 a supply current 3 ta = 25 c ? i dd ? 3-2 v dd = 5.0 v, 600 a ta = 50 c ? i dd ? 4-1 v dd = 5.0 v, 450 650 a supply current 4 ta = 25 c ? i dd ? 4-2 v dd = 5.0 v, 700 a ta = 50 c ? i dd ? 5-1 v dd = 5.0 v, 500 700 a supply current 5 ta = 25 c ? i dd ? 5-2 v dd = 5.0 v, 750 a ta = 50 c ? i dd ? 6-1 v dd = 5.0 v, 700 900 a supply current 6 ta = 25 c ? i dd ? 6-2 v dd = 5.0 v, 1000 a ta = 50 c oscillator correction capacitance cd v dd = 5.0 v, xtout pin (built-in) 16 20 24 pf cf oscillator specifications, cf: 4000 khz, ccg = ccd = 33 pf, halt mode, figure 8 cf oscillator specifications, cf: 2000 khz, ccg = ccd = 33 pf, halt mode, figure 8 cf oscillator specifications, cf: 1000 khz, ccg = ccd = 100 pf, halt mode, figure 8 or 220 pf cf oscillator specifications, cf: 400 khz, ccg = ccd = 330 pf, halt mode, figure 7 crystal oscillator specifications, crystal: 38 or 65 khz, cg = 10 pf, c1 = 25 k , halt mode, figure 6, lcd = 1/3 bias crystal oscillator specifications, crystal: 32 khz cg = 20 pf, c1 = 25 k , halt mode, figure 6, lcd = 1/3 bias s1 to s4, k1 to k4, m1 to m4, so1 to so4, a1 to a4, int, res (with the k, p, m, so and a ports in input mode and with open specifications for the int and res pins)
figure 1-1 oscillator circuit (xt pins) figure 1-2 oscillator circuit (cf pins) figure 2 s, k, p, m, so and a port input circuit configuration recommended ceramic filters no. 4435- 26 /29 lc587008, 587006, 587004 manufacturer murata mfg. co., ltd. kyocera corporation item catalog no. ccg (pf) ccd (pf) catalog no. ccg (pf) ccd (pf) frequency 400 khz csb400p 330 330 kbr-400b 330 330 800 khz csb800j 220 220 kbr-800h 100 100 1 mhz csb1000j 220 220 kbr-1000h/y 100 100 2 mhz csa2.00mg, cst2.00mg 33 (built-in) 33 (built-in) kbr-2.0ms 33 33 4 mhz csa4.00mg, csa4.00mgw 33 (built-in) 33 (built-in) kbr-4.0msa/mca, 33 (built-in) 33 (built-in) kbr-4.0mks/mws figure 3 supply leakage test circuit figure 4 output voltage test circuit stopped state s-port input resistors: on state i/o ports: output mode, all data values high res and int pins: built-in resistor specifications, open state currents due to external components connected to the lcd ports are not included. crystal frequency: between 32 and 65 khz cf frequency: 200 khz to 4 mhz crystal frequency: 32 khz c1, c2 and c3: 0.1 f figures 4 and 5 lcd ports: open cf frequency: 200 khz to 4 mhz
figure 5 output voltage test circuit figure 7 supply current test circuit figure 9 supply current test circuit figure 6 supply current test circuit figure 8 supply current test circuit figure 10 supply current test circuit no. 4435- 27 /29 lc587008, 587006, 587004 figure 11 segment pin open drain circuit configurations
figure 13 serial i/o timing (in external clock mode) figure initial reset timing figure 14 timer 1 and timer 2 external clock input timing (external clock mode, pins m3 and m4) no. 4435- 28 /29 lc587008, 587006, 587004 figure 12 sample rc oscillator frequency characteristics
ps no. 4435- 29 /29 lc587008, 587006, 587004 this catalog provides information as of june, 1995. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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